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Optimization of test-access architecture and test scheduling for 3D ICs

dc.contributor.authorDeutsch, Sergej
dc.contributor.authorNoia, Brandon
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-27T08:46:40Z
dc.date.available2021-10-27T08:46:40Z
dc.date.issued2019-03
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32881
dc.sourceIIOimport
dc.titleOptimization of test-access architecture and test scheduling for 3D ICs
dc.typeBook chapter
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage281
dc.source.bookHandbook of 3D Integration - Volume 4: 3D Design, Test, and Thermal Management
dc.source.endpage300
dc.identifier.urlhttps://doi.org/10.1002/9783527697052.ch13
imec.availabilityPublished - imec


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