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Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

dc.contributor.authorFan, Xin
dc.contributor.authorStuijt, Jan
dc.contributor.authorLiu, Bo
dc.contributor.authorGemmeke, Tobias
dc.date.accessioned2021-10-27T09:08:38Z
dc.date.available2021-10-27T09:08:38Z
dc.date.issued2019
dc.identifier.issn1549-8328
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32949
dc.sourceIIOimport
dc.titleSynthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT
dc.typeJournal article
dc.contributor.imecauthorStuijt, Jan
dc.contributor.orcidimecStuijt, Jan::0000-0001-6797-2339
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage941
dc.source.endpage954
dc.source.journalIEEE Transactions on Circuits and Systems I Regular Papers
dc.source.issue3
dc.source.volume66
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8493543
imec.availabilityPublished - open access


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