dc.contributor.author | Renukaswamy, Pratap | |
dc.contributor.author | Markulic, Nereo | |
dc.contributor.author | Wambacq, Piet | |
dc.contributor.author | Craninckx, Jan | |
dc.date.accessioned | 2021-10-29T02:59:45Z | |
dc.date.available | 2021-10-29T02:59:45Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 0018-9200 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/35828 | |
dc.source | IIOimport | |
dc.title | A 12mW 10 GHz FMCW PLL based on an integrating DAC with 28 kHz rms-frequency-error for 23 MHz/ s slope and 1.2 GHz chirp-bandwidth | |
dc.type | Journal article | |
dc.contributor.imecauthor | Renukaswamy, Pratap | |
dc.contributor.imecauthor | Markulic, Nereo | |
dc.contributor.imecauthor | Wambacq, Piet | |
dc.contributor.imecauthor | Craninckx, Jan | |
dc.contributor.orcidimec | Renukaswamy, Pratap::0000-0003-4148-7188 | |
dc.contributor.orcidimec | Markulic, Nereo::0000-0001-6691-4647 | |
dc.contributor.orcidimec | Wambacq, Piet::0000-0003-4388-7257 | |
dc.contributor.orcidimec | Craninckx, Jan::0000-0002-3980-0203 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 3294 | |
dc.source.endpage | 3307 | |
dc.source.journal | IEEE Journal of Solid-State Circuits | |
dc.source.issue | 12 | |
dc.source.volume | 55 | |
dc.identifier.url | https://ieeexplore.ieee.org/document/9197684 | |
imec.availability | Published - imec | |