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Analysis of a 28-nm CMOS fast-lock bang-bang digital PLL with 220-fs RMS jitter for millimeter-wave communication

dc.contributor.authorTsai, Cheng-Hsueh
dc.contributor.authorZong, Zhiwei
dc.contributor.authorPepe, Federico
dc.contributor.authorMangraviti, Giovanni
dc.contributor.authorCraninckx, Jan
dc.contributor.authorWambacq, Piet
dc.date.accessioned2021-10-29T05:32:08Z
dc.date.available2021-10-29T05:32:08Z
dc.date.issued2020
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/36085
dc.sourceIIOimport
dc.titleAnalysis of a 28-nm CMOS fast-lock bang-bang digital PLL with 220-fs RMS jitter for millimeter-wave communication
dc.typeJournal article
dc.contributor.imecauthorTsai, Cheng-Hsueh
dc.contributor.imecauthorZong, Zhiwei
dc.contributor.imecauthorMangraviti, Giovanni
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecZong, Zhiwei::0000-0001-6748-2153
dc.contributor.orcidimecMangraviti, Giovanni::0000-0001-5134-7205
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.identifier.doi10.1109/JSSC.2020.2993717
dc.source.peerreviewyes
dc.source.beginpage1854
dc.source.endpage1863
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.issue7
dc.source.volume55
imec.availabilityPublished - imec


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