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Impact of Back-End-Of-Line architecture on chip-package-interaction in advanced interconnects

dc.contributor.authorVanstreels, Kris
dc.contributor.authorZahedmanesh, Houman
dc.contributor.authorGonzalez, Mario
dc.date.accessioned2021-10-29T06:51:25Z
dc.date.available2021-10-29T06:51:25Z
dc.date.issued2020
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/36214
dc.sourceIIOimport
dc.titleImpact of Back-End-Of-Line architecture on chip-package-interaction in advanced interconnects
dc.typeJournal article
dc.contributor.imecauthorVanstreels, Kris
dc.contributor.imecauthorZahedmanesh, Houman
dc.contributor.imecauthorGonzalez, Mario
dc.contributor.orcidimecVanstreels, Kris::0000-0002-4420-0966
dc.source.peerreviewyes
dc.source.beginpage113825-1
dc.source.endpage113825-9
dc.source.journalMicroelectronics Reliability
dc.source.volume112
dc.identifier.urlhttps://doi.org/10.1016/j.microrel.2020.113825
imec.availabilityPublished - imec


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