A 12 Bit 4.7-MS/s 260.5-mu W Digital Feed-Forward Incremental-Sigma Delta-SAR ADC in 0.13-mu m CMOS for Image Sensors

Abstract

This paper presents a 12 bit, 4.7 MS/s Digital Feed-Forward Incremental Sigma Delta-Successive Approximation Register (DFF I-Sigma Delta-SAR) Analog-to-Digital Converter (ADC) for column readout of image sensors. An input range detection phase and a new switching scheme for the DAC in the first stage allow reaching the desired 4 bit resolution of the I-Sigma Delta stage with an Over Sampling Ratio (OSR) of 8. A second stage SAR converts the I-Sigma Delta residue voltage resolving the 8 Least Significant Bits (LSBs). The ADC is integrated in a test chip with a Source Follower (SF) test unit that emulates a pixel array and is fabricated using 2-Poly-4-Metal 130 nm CMOS technology. The ADC operates under 3.3 V/1.2 V supply voltages, achieving a DNL of -0.43/0.62 12 bit LSBs, 356 mu V rms noise, equivalent to 9.2 bit ENOB at a sampling frequency of 4.7 MS/s with an OSR of 8. The proposed ADC consumes 260.5 mu W of power, yielding a Walden Figure-of-Merit 94 fJ/c.s.. The core area is 18400 mu m(2).