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A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs
dc.contributor.author | Irmak, Hasan | |
dc.contributor.author | Corradi, Federico | |
dc.contributor.author | Detterer, Paul | |
dc.contributor.author | Alachiotis, Nikolaos | |
dc.contributor.author | Ziener, Daniel | |
dc.date.accessioned | 2021-11-02T15:56:41Z | |
dc.date.available | 2021-11-02T15:56:41Z | |
dc.date.issued | 2021-SEP | |
dc.identifier.other | WOS:000702371900001 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/37533 | |
dc.source | WOS | |
dc.title | A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs | |
dc.type | Journal article | |
dc.contributor.imecauthor | Corradi, Federico | |
dc.contributor.imecauthor | Detterer, Paul | |
dc.contributor.orcidext | Alachiotis, Nikolaos::0000-0001-8162-3792 | |
dc.contributor.orcidimec | Corradi, Federico::0000-0002-5868-8077 | |
dc.contributor.orcidimec | Detterer, Paul::0000-0001-9329-1721 | |
dc.identifier.doi | 10.3390/jlpea11030032 | |
dc.source.numberofpages | 25 | |
dc.source.peerreview | yes | |
dc.source.journal | JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS | |
dc.source.issue | 3 | |
dc.source.volume | 11 | |
imec.availability | Under review |
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