Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

Abstract

The endurance of the HfO2-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (T-ramp), which is the time to reach the PG/ER voltage, and the hold time (T-hold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10(4) by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long T-ramp but short T-hold are desirable to suppress the interface trap generation in FeFET. The relation between T-ramp, T-hold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).