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Interface admittance measurement and simulation of dual gated CVD WS2 MOSCAPs: Mapping the D-IT(E) profile

dc.contributor.authorMootheri, Vivek
dc.contributor.authorWu, Xiangyu
dc.contributor.authorCott, Daire
dc.contributor.authorGroven, Benjamin
dc.contributor.authorHeyns, Marc
dc.contributor.authorAsselberghs, Inge
dc.contributor.authorRadu, Iuliana
dc.contributor.authorLin, Dennis
dc.date.accessioned2021-11-02T15:59:51Z
dc.date.available2021-11-02T15:59:51Z
dc.date.issued2021-SEP
dc.identifier.issn0038-1101
dc.identifier.otherWOS:000672563600014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37791
dc.sourceWOS
dc.titleInterface admittance measurement and simulation of dual gated CVD WS2 MOSCAPs: Mapping the D-IT(E) profile
dc.typeJournal article
dc.contributor.imecauthorMootheri, Vivek
dc.contributor.imecauthorWu, Xiangyu
dc.contributor.imecauthorCott, Daire
dc.contributor.imecauthorGroven, Benjamin
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorAsselberghs, Inge
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorLin, Dennis
dc.contributor.orcidimecGroven, Benjamin::0000-0002-5781-7594
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.identifier.doi10.1016/j.sse.2021.108035
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.journalSOLID-STATE ELECTRONICS
dc.source.volume183
imec.availabilityUnder review


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220.500.12860/37791.22023-01-05T14:29:10Zvalidation by library/open access desk
120.500.12860/37791*2021-11-02T15:59:51Z

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