High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors

Abstract

Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.