mu Brain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

Abstract

The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present mu Brain: the first digital yet fully event-driven without clock architecture, with co-located memory and processing capability that exploits event-based processing to reduce an always-on system's overall energy consumption (mu W dynamic operation). The chip area in a 40 nm Complementary Metal Oxide Semiconductor (CMOS) digital technology is 2.82 mm(2) including pads (without pads 1.42 mm(2)). This small area footprint enables mu Brain integration in re-trainable sensor ICs to perform various signal processing tasks, such as data preprocessing, dimensionality reduction, feature selection, and application-specific inference. We present an instantiation of the mu Brain architecture in a 40 nm CMOS digital chip and demonstrate its efficiency in a radar-based gesture classification with a power consumption of 70 mu W and energy consumption of 340 nJ per classification. As a digital architecture, mu Brain is fully synthesizable and lends to a fast development-to-deployment cycle in Application-Specific Integrated Circuits (ASIC). To the best of our knowledge, mu Brain is the first tiny-scale digital, spike-based, fully parallel, non-Von-Neumann architecture (without schedules, clocks, nor state machines). For these reasons, mu Brain is ultra-low-power and offers software-to-hardware fidelity. mu Brain enables always-on neuromorphic computing in IoT sensor nodes that require running on battery power for years.