Total-Ionizing-Dose Response of Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors

Abstract

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes.