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Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
dc.contributor.author | Zhou, Longda | |
dc.contributor.author | Liu, Qianqian | |
dc.contributor.author | Yang, Hong | |
dc.contributor.author | Ji, Zhigang | |
dc.contributor.author | Xu, Hao | |
dc.contributor.author | Wang, Guilei | |
dc.contributor.author | Simoen, Eddy | |
dc.contributor.author | Jiang, Haojie | |
dc.contributor.author | Luo, Ying | |
dc.contributor.author | Kong, Zhenzhen | |
dc.contributor.author | Bai, Guobin | |
dc.contributor.author | Luo, Jun | |
dc.contributor.author | Yin, Huaxiang | |
dc.contributor.author | Zhao, Chao | |
dc.contributor.author | Wang, Wenwu | |
dc.date.accessioned | 2021-11-02T16:04:10Z | |
dc.date.available | 2021-11-02T16:04:10Z | |
dc.date.issued | 2021 | |
dc.identifier.issn | 2168-6734 | |
dc.identifier.other | WOS:000622098400034 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/38115 | |
dc.source | WOS | |
dc.title | Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization | |
dc.type | Journal article | |
dc.contributor.imecauthor | Simoen, Eddy | |
dc.contributor.orcidext | Zhou, Longda::0000-0001-8969-1458 | |
dc.contributor.orcidimec | Simoen, Eddy::0000-0002-5218-4046 | |
dc.identifier.doi | 10.1109/JEDS.2021.3057662 | |
dc.source.numberofpages | 7 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 229 | |
dc.source.endpage | 235 | |
dc.source.journal | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | |
dc.source.volume | 9 | |
imec.availability | Under review |
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