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Articles
Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
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Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
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Date
2021
Journal article
https://doi.org/10.1109/JEDS.2021.3057662
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Zhou, Longda
;
Liu, Qianqian
;
Yang, Hong
;
Ji, Zhigang
;
Xu, Hao
;
Wang, Guilei
;
Simoen, Eddy
;
Jiang, Haojie
;
Luo, Ying
;
Kong, Zhenzhen
;
Bai, Guobin
;
Luo, Jun
;
Yin, Huaxiang
;
Zhao, Chao
;
Wang, Wenwu
Journal
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
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421
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1659
since deposited on 2021-11-02
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last week
Acq. date: 2026-01-08
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Metrics
Downloads
421
since deposited on 2021-11-02
56
last month
11
last week
Acq. date: 2026-01-08
Views
1659
since deposited on 2021-11-02
1
last month
1
last week
Acq. date: 2026-01-08
Citations