Publication:

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Date

2021
Journal article
https://doi.org/10.1109/JEDS.2021.3057662
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dc.contributor.authorZhou, Longda
dc.contributor.authorLiu, Qianqian
dc.contributor.authorYang, Hong
dc.contributor.authorJi, Zhigang
dc.contributor.authorXu, Hao
dc.contributor.authorWang, Guilei
dc.contributor.authorSimoen, Eddy
dc.contributor.authorJiang, Haojie
dc.contributor.authorLuo, Ying
dc.contributor.authorKong, Zhenzhen
dc.contributor.authorBai, Guobin
dc.contributor.authorLuo, Jun
dc.contributor.authorYin, Huaxiang
dc.contributor.authorZhao, Chao
dc.contributor.authorWang, Wenwu
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidextZhou, Longda::0000-0001-8969-1458
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.accessioned2022-07-07T15:41:36Z
dc.date.available2021-11-02T16:04:10Z
dc.date.available2022-07-07T15:41:36Z
dc.date.issued2021
dc.identifier.doi10.1109/JEDS.2021.3057662
dc.identifier.issn2168-6734
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38115
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage229
dc.source.endpage235
dc.source.issuena
dc.source.journalIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
dc.source.numberofpages7
dc.source.volume9
dc.title

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

dc.typeJournal article
dspace.entity.typePublication
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