Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Zhou, Longda; Liu, Qianqian; Yang, Hong; Ji, Zhigang; Xu, Hao; Wang, Guilei; Simoen, Eddy; Jiang, Haojie; Luo, Ying; Kong, Zhenzhen; Bai, Guobin; Luo, Jun; Yin, Huaxiang; Zhao, Chao; Wang, Wenwu

doi:10.1109/JEDS.2021.3057662

Simple item page Full metadata Statistics

Files

Published version 2.25 MB

Author(s)

;

;

;

;

;

;

;

;

;

;

;

;

;

;

Journal

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY

Metrics

365 since deposited on 2021-11-02

53last month

8last week

Acq. date: 2025-12-08

1658 since deposited on 2021-11-02

Acq. date: 2025-12-08

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Date

Files

Author(s)

Journal

Abstract

Description

Metrics

Downloads

Views

Citations

Metrics

Downloads

Views

Citations