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Event-Based Verification of Synchronous, Globally Controlled, Logic Designs Against Signal Flow Graphs

dc.contributor.authorVan Aelten, Filip
dc.contributor.authorAllen, J.
dc.contributor.authorDevadas, S.
dc.date.accessioned2021-09-29T12:49:12Z
dc.date.available2021-09-29T12:49:12Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/384
dc.sourceIIOimport
dc.titleEvent-Based Verification of Synchronous, Globally Controlled, Logic Designs Against Signal Flow Graphs
dc.typeJournal article
dc.source.peerreviewno
dc.source.beginpage122
dc.source.endpage134
dc.source.journalIEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
dc.source.issue1
dc.source.volume13
imec.availabilityPublished - imec


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