Implication of Channel Percolation in Ferroelectric FETs for Threshold Voltage Shift Modeling

Abstract

Unraveling the gate bias dependence of threshold voltage (V-TH) shift in hafnia-based FeFETs is a central element to device design and reliable operation. Here we present a domain-percolation-based ferroelectric (FE) V-TH shift model, in which we attribute the FE-induced VTH lowering to the source-to-drain "clustering" of successively flipped-up FE domains, as the global polarization increases with the gate bias. We highlight our accurate, semi-quantitative modeling reproduction of the experimental V-TH shift in our Hf0.5Zr0.5O2 n-FeFET hardware in the presence of traps, where a turnaround of V-TH shift versus gate bias is observed. We argue that the turnaround occurs because the FE V-TH lowering only starts to prevail when the gate bias has flipped up enough FE domains to "cluster" from source to drain, before which V-TH keeps increasing with the gate bias due to charge trapping. The trapping behavior is simulated by a two-state non-radiative multi-phonon model. We further predict that the downscaling of gate length (L-g) can facilitate the onset of percolation in FE layer, which intrinsically helps to reduce the FE programming voltage (VPGM, by similar to 0.8V when ideal, trap-free) in FeFETs.