The Complementary FET (CFET) 6T-SRAM

Abstract

This article discusses complementary FET (CFET)-based static random access memory (SRAM) to achieve next-generation bitcell area scaling and performance gain in advanced CMOS technology nodes. SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are mandatory to continue SRAM scaling with technology advancement. The CFET reduces the SRAM bitcell area by folding nMOS over pMOS and making SRAM cross-coupled connections in the middle end of line (MEOL). The compact bitcell offers large area scaling combined with lowering bitline and wordline resistance. Lower parasitic resistance improves SRAM write margin and performance. The CFET SRAM cell area, write margin, read margin, and performance are evaluated and compared with FinFET (FF)-based SRAM. The CFET 111 and 122 SRAM provides up to 43.75% and 35% area gain w.r.t. FF 111 and 122 SRAM, respectively. Moreover, the CFET 122 SRAM has 11% faster read operation than FF 122 SRAM, respectively.