Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Abstract

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (V-BG) is applied only during ON-state and a constant front-gate stress V-G is used, BTI reliability is not influenced by the applied V-BG (due to its negligible impact on the front-gate oxide field, E-ox). Therefore, supplying an FBB during ON-state can be used to adjust device performance-asVBG modulates the channel current through Vth and mobility-without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress V-ov is maintained by adjusting the front-gate V-G [i.e., V-G-Vth(VBG) is kept constant under different V-BG's], the BTI reliability can be improved under FBB (due to a reduced E-ox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation.