Large-Scale 2D Spin-Based Quantum Processor with a Bi-Linear Architecture

Abstract

Here, we propose a bi-linear 2D device architecture for the demonstration of large-scale silicon-based quantum computers. Based on extensive modeling of the structure with multiphysics techniques, we report critical dimensions, quantum gate times, fidelities, and quantum-chip resources for error correction. The design is compact, can be realized with current CMOS fabrication technology, and allows planar integration of the control lines for the quantum bits, thereby providing a straightforward route for large-scale silicon quantum computers.