Overlay challenges in 3D heterogeneous integration

Abstract

3D heterogeneous integration is an evolving segment of the world semiconductor industry roadmap to enable improvements in device performance beyond Moore's law expectations. These "More than Moore" (MtM) performance enhancements have the potential for realizing dramatic improvements in communication bandwidth, design flexibility that enables new system architectures on-chip or at the wafer level, and overall cost reduction. 3D heterogeneous integration strives to increase electrical connectivity through pitch and contact dimensional scaling to enable <10 mu m pitch solder bump scaling, and sub-micrometer hybrid Cu/dielectric fusion bond connectivity. Integration options include wafer to wafer (W2W), pick-and-place (P&P), and die to wafer (D2W) assembly strategies. Enhanced process capability and systems architecture imposes new overlay (OVL) metrology challenges to address variable silicon substrate thickness, stressinduced wafer or die distortions, and tight OVL error specifications. In this work, we will cover the OVL trends and challenges surrounding this evolving segment. We will cover different OVL aspects such as accuracy, measurability, reproducibility, and throughput and discuss their impact on pre and post-bonding error budgets.