Dry Etching of III-V Layers for Monolithic Optical Device Fabrication on Si

Abstract

Several steps of III-V layer etching have been developed to enable monolithic GaAs-based optical device integration on top of 300 mm silicon wafers by using a conventional CMOS p-line tool set. Three separate cases are covered, namely: contact etch, trench etch, and deep cut of III-V nano-ridges. It has been shown that a methane-based plasma in combination with oxygen-based flash can be used in cycles to preform III-V etching of the structures. A small-scale DOE has been performed for the deep cut process (700 nm deep) in terms of ESC temperature variation and based on the roughness minimization criteria the best process has been selected. The facet angle of such cut process affects optical device performance, so it has been taken as another important parameter of DOE, which has been kept at ~12 degree by following the patterning approach selected. Finally, all these III-V patterning modules are essential for the monolithic integration of various III-V nano-ridge optical components with silicon photonics.