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DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets

dc.contributor.authorCretu, B.
dc.contributor.authorVeloso, A.
dc.contributor.authorSimoen, E.
dc.date.accessioned2022-10-30T02:55:18Z
dc.date.available2022-10-30T02:55:18Z
dc.date.issued2022-AUG
dc.identifier.issn0038-1101
dc.identifier.otherWOS:000868453300006
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40657
dc.sourceWOS
dc.titleDC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets
dc.typeJournal article
dc.contributor.imecauthorVeloso, A.
dc.contributor.imecauthorSimoen, E.
dc.identifier.doi10.1016/j.sse.2022.108360
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.journalSOLID-STATE ELECTRONICS
dc.source.volume194
imec.availabilityUnder review


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VersionItemDateSummary
220.500.12860/40657.22022-11-17T16:00:35Zvalidation by library/open access desk
120.500.12860/40657*2022-10-30T02:55:18Z

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