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DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets
dc.contributor.author | Cretu, B. | |
dc.contributor.author | Veloso, A. | |
dc.contributor.author | Simoen, E. | |
dc.date.accessioned | 2022-10-30T02:55:18Z | |
dc.date.available | 2022-10-30T02:55:18Z | |
dc.date.issued | 2022-AUG | |
dc.identifier.issn | 0038-1101 | |
dc.identifier.other | WOS:000868453300006 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/40657 | |
dc.source | WOS | |
dc.title | DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets | |
dc.type | Journal article | |
dc.contributor.imecauthor | Veloso, A. | |
dc.contributor.imecauthor | Simoen, E. | |
dc.identifier.doi | 10.1016/j.sse.2022.108360 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.journal | SOLID-STATE ELECTRONICS | |
dc.source.volume | 194 | |
imec.availability | Under review |
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