Show simple item record

Modeling data flow and control flow for digital signal processing system synthesis

dc.contributor.authorVan Swaaij, Michael
dc.contributor.authorFranssen, Frank
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-09-29T12:50:20Z
dc.date.available2021-09-29T12:50:20Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/406
dc.sourceIIOimport
dc.titleModeling data flow and control flow for digital signal processing system synthesis
dc.typeBook chapter
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage219
dc.source.bookVLSI Design Methodologies for DSP Architectures and Applications
dc.source.endpage259
imec.availabilityPublished - open access


Files in this item

Thumbnail
Name:
401.pdf
Size:
439.8Kb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record