III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance

Abstract

In this paper, we demonstrate III-V HBTs fabricated on GaAs/InGaP layers realized by merging the nano-ridges to create a bulk-like stack on a 300 mm Si substrate. The emitter-base and base-collector diodes show an ideality factor of similar to 1.2 and similar to 2.0, respectively. A maximum DC current gain of similar to 120 and breakdown voltage, BVCBO, of 10 V is achieved at Ft similar to 17GHz. A direct correlation between threading dislocation density (TDD) and various device metrics is shown using DC, RF and reliability measurements. Furthermore, 3D Monte Carlo simulations were done to model and understand the impact of different types of merged structures on the thermal performance of the device. With this work, we show the potential of merged nano-ridges, in enabling an efficient hybrid III-V/CMOS technology for mm-wave applications, as a material-independent tool to understand the impact of defects on the performance of III-V devices.