An AC-Coupled 1st-Order ?-?S Readout IC for Area-Efficient Neural Signal Acquisition

Abstract

The current demand for high-channel-count neural-recording interfaces calls for more area-and power-efficient readout architectures that do not compromise other electrical performances. In this article, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range, and electrode dc offset (EDO) cancellation. An ac-coupled 1st-order digitally-intensive delta-delta sigma architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits, and a digital control, has been fabricated in 22-nm fully depleted silicon on insulator (FDSOI) CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 mu W, and an input-referred noise of 7.7 +/- 0.4 mu Vrms in the AP band and 11.9 +/- 1.1 mu Vrms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.