Dedicated ICs for the Characterization of Variability and Aging Studies and their Use in Lightweight Security Applications

Abstract

With today's rapid development of novel and advanced technology nodes, transistor degradation phenomena like BTI and HCI are evolving to an even more serious concern for analog and digital circuit designers. Besides, time-dependent variability effects like TDDB and transient effects like RTN, which can cause significant performance deviations or even a total circuit failure, can alternatively be used for security applications such as physical unclonable functions. In this context, it is fundamental to accurately model variability and degradation which requires elaborate statistical characterization of these phenomena. To avoid the long testing times that such characterization would otherwise imply, the test circuits should allow the parallelization of stress application. This paper presents a test framework based on the utilization of transistor and circuit arrays that allows the time-efficient testing of degradation phenomena.