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dc.contributor.authorSateesan, Arish
dc.contributor.authorBiesmans, Jelle
dc.contributor.authorClaesen, Thomas
dc.contributor.authorVliegen, Jo
dc.contributor.authorMentens, Nele
dc.date.accessioned2023-06-29T14:13:21Z
dc.date.available2023-03-29T03:54:08Z
dc.date.available2023-06-29T14:13:21Z
dc.date.issued2023
dc.identifier.issn0141-9331
dc.identifier.otherWOS:000946702600001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41401.2
dc.sourceWOS
dc.titleOptimized algorithms and architectures for fast non-cryptographic hash functions in hardware
dc.typeJournal article
dc.identifier.doi10.1016/j.micpro.2023.104782
dc.source.numberofpages11
dc.source.peerreviewyes
dc.source.beginpageArt.: 104782
dc.source.endpagena
dc.source.journalMICROPROCESSORS AND MICROSYSTEMS
dc.source.issueApril
dc.source.volume98
imec.availabilityPublished - imec
dc.description.wosFundingTextThis work is supported by the ESCALATE project, funded by FWO, Belgium (G0E0719N) and SNSF, Switzerland (200021L_182005) , and by Cybersecurity Research Flanders, Belgium (VR20192203) .


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