Cryo-Computing for Infrastructure Applications: A Technology-to-Microarchitecture Co-optimization Study

Abstract

Cryo-computing has been proposed for data center and HPC applications. Ultra-low temperature CMOS not only has the potential to aid the node-to-node performance-power improvement despite cooling overhead but can also alleviate the thermal challenges in modern designs realized at advanced technology nodes. This paper presents a system-technology co-optimization of cryogenic designs (100-150K) to achieve a 16X performance-per-watt gain. Device and circuit-level optimizations for logic and memory circuits are showcased, and an alternate cryo-enabled eDRAM memory is studied in addition to classical SRAM memory. A standard VLSI design flow is used to design a microprocessor at 100-150K, and a system-level study and microarchitecture optimization is performed for cryogenic operation and boost IPC. At best, 12X, and 16X, performance/ watt can be achieved at the CPU and system level, respectively at a projected cooling cost of 4X.