dc.contributor.author | Mathur, R. | |
dc.contributor.author | Bhargava, M. | |
dc.contributor.author | Cline, B. | |
dc.contributor.author | Salahuddin, Shairfe Muhammad | |
dc.contributor.author | Gupta, Anshul | |
dc.contributor.author | Schuddinck, Pieter | |
dc.contributor.author | Ryckaert, Julien | |
dc.contributor.author | Kulkarni, J.P. | |
dc.date.accessioned | 2023-06-20T13:38:04Z | |
dc.date.available | 2023-06-20T10:36:07Z | |
dc.date.available | 2023-06-20T13:38:04Z | |
dc.date.issued | 2022 | |
dc.identifier.issn | 0018-9383 | |
dc.identifier.other | WOS:000751496100001 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/41927.2 | |
dc.source | WOS | |
dc.title | Buried Interconnects for Sub-5 nm SRAM Design | |
dc.type | Journal article | |
dc.contributor.imecauthor | Salahuddin, Shairfe Muhammad | |
dc.contributor.imecauthor | Gupta, Anshul | |
dc.contributor.imecauthor | Schuddinck, Pieter | |
dc.contributor.imecauthor | Ryckaert, Julien | |
dc.contributor.orcidext | Mathur, R.::0000-0002-8064-5612 | |
dc.contributor.orcidimec | Salahuddin, S.::0000-0002-6483-8430 | |
dc.contributor.orcidimec | Salahuddin, Shairfe Muhammad::0000-0002-6483-8430 | |
dc.contributor.orcidimec | Schuddinck, Pieter::0000-0003-1893-3135 | |
dc.identifier.doi | 10.1109/TED.2022.3143078 | |
dc.source.numberofpages | 7 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 1041 | |
dc.source.endpage | 1047 | |
dc.source.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | |
dc.source.issue | 3 | |
dc.source.volume | 69 | |
imec.availability | Published - imec | |
dc.description.wosFundingText | The 5-nm technology files and simulation models were provided by imec. Tool support for extraction was provided by Synopsys. | |