Power, Performance, Area, and Cost Analysis of Face-to-Face-Bonded 3-D ICs

Abstract

This article presents a power, performance, area, and cost (PPAC) analysis for large-scale 3-D processor designs based on face-to-face wafer-to-wafer (W2W) and collective die-to-wafer (Co-D2W) bonding technologies. From evaluating our cost model on a comprehensive portfolio of technology nodes, we investigate a typically disregarded opportunity in 3-D through diverse computer-age statistical methods: area savings due to buffer savings and better routability, offering unforeseen, and considerable cost savings. We explore the viability of this factor with the feedback of a state-of-the-art 3-D memory-on-logic implementation flow. We show how this affects the PPAC of full-chip GDS implementations of a large-scale manycore processor design. Experiments show that our memory-on-logic 3-D implementation offers 7% silicon area savings, resulting in a 53.5% footprint reduction. We also obtained a 40% power-performance-cost improvement compared with the 2-D counterparts.