Improving the Tamper-Aware Odometer Concept by Enhancing Dynamic Stress Operation

Abstract

On-chip degradation monitors have recently gained significant relevance because they can provide real-time estimations of IC reliability by exploiting the fundamental physics of BTI and HCD circuit degradation. Moreover, this type of degradation monitors can be used as a tamper detection mechanism to expose counterfeited chips, as we have demonstrated previously. In this context, common ring-oscillator (RO)-based odometers have shown a predominant BTI component over HCD in dynamic stress. This complicates the effort of combining the different degradation kinetics of monitors stressed solely with BTI and HCD for accurate aging determination and counterfeiting detection capability. In this work, we propose and validate two new RO-based odometers to enhance HCD over BTI degradation by (i) a RO with a high order harmonic trigger circuitry and (ii) a RO with I/O pass gates utilized to perform DC HCD. We also extend the tamper-aware odometer concept to a commercial 16 nm FinFET technology with ROs to further exploit the larger HCD component in FinFET technology. Finally, we present not only accelerated degradation tests but also on-chip circuit annealing by means of dedicated on-chip heaters and off-chip furnace anneal. From our findings, we derive an optimal combination of odometers to accurately account for IC age and for a robust tamper-aware monitors combination.