dc.contributor.author | Acharya, Lomash Chandra | |
dc.contributor.author | Sharma, Arvind | |
dc.contributor.author | Mishra, Neeraj | |
dc.contributor.author | Singh, Khoirom Johnson | |
dc.contributor.author | Dargupally, Mahipal | |
dc.contributor.author | Shabarish, Nayakanti Sai | |
dc.contributor.author | Mandal, Ajoy | |
dc.contributor.author | Ramakrishnan, Venkatraman | |
dc.contributor.author | Dasgupta, Sudeb | |
dc.contributor.author | Bulusu, Anand | |
dc.date.accessioned | 2023-10-17T13:10:05Z | |
dc.date.available | 2023-08-11T16:46:01Z | |
dc.date.available | 2023-10-17T13:10:05Z | |
dc.date.issued | 2023 | |
dc.identifier.issn | 0278-0070 | |
dc.identifier.other | WOS:001033520500018 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/42321.2 | |
dc.source | WOS | |
dc.title | Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort | |
dc.type | Journal article | |
dc.contributor.imecauthor | Sharma, Arvind | |
dc.contributor.orcidimec | Sharma, Arvind::0000-0002-9250-9642 | |
dc.date.embargo | 9999-12-31 | |
dc.identifier.doi | 10.1109/TCAD.2022.3231173 | |
dc.source.numberofpages | 7 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 2657 | |
dc.source.endpage | 2663 | |
dc.source.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | |
dc.source.issue | 8 | |
dc.source.volume | 42 | |
imec.availability | Published - imec | |
dc.description.wosFundingText | his work was supported by the Semiconductor Research Corporation (SRC) under IRP task-2864.001. | |