Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis

Abstract

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with limited overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. The FPGA design generated by HLS achieved the same performance as compared to its HDL counterpart when deployed on a System-on-Chip (SoC)-based SDR, as verified by a professional wireless connectivity tester.