A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

Abstract

A 16-GHz charge-pump phase-locked loop (CP-PLL) for a robust duty-cycled frequency-modulated continuous-wave (FMCW) radar chirp generation is presented. A duty-cycling (DC) scheme is introduced to reduce the overall power consumption. To enable fast startup and fast locking, a two-point modulated CP-PLL frequency modulator is designed. To enable the two-point gain mismatch calibration a time-domain sign extraction technique is explored. The 16-GHz chirp generator achieves a 29.3-MHz/mu s chirp slope with 41-kHz rms-frequency error for 1.5-GHz chirp bandwidth while consuming 16.5-mW power. The modulator can be used in a heavily duty-cycled regime, due to its robust below 1-mu s phase-locked loop (PLL) phase/frequency lock time.