Thermal modeling of hybrid three-dimensional integrated, ring-based silicon photonic-electronic transceivers

Abstract

Co-packaged optics for high performance computing or other data center applications requires dense integration of silicon photonic integrated circuits (PICs) with electronic integrated circuits (EICs). This work discusses the impact of three-dimensional (3D) hybrid integration on the thermal performance of Si ring-based photonic devices in wavelength-division multiplexing PICs. A thermal finite element model of the EIC-PIC assembly is developed and calibrated with thermo-optic device measurements, before and after integration of an electrical driver on top of the PIC by means of microbump flip-chip bonding. Both measurements and simulations of the thermal tuning efficiency and crosstalk between silicon photonic devices show that the EIC can have a significant impact on the thermal performance of the integrated heaters in the PIC by acting as an undesired heat spreader. This heat spreading lowers the heater efficiency with 43.3% and increases the thermal crosstalk between the devices by up to 44.4% compared with a PIC-only case. Finally, it is shown that these negative thermal effects of 3D integration can largely be mitigated by a thermally aware design of the microbump array and the back-end-of-line interconnect, guided by the calibrated thermal simulation model.