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Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices

dc.contributor.authorSamudra, G.
dc.contributor.authorKrishnasamy, Rajendran
dc.date.accessioned2021-10-14T13:42:35Z
dc.date.available2021-10-14T13:42:35Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4717
dc.sourceIIOimport
dc.titleComparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices
dc.typeJournal article
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage513
dc.source.endpage530
dc.source.journalInternational Journal of Electronics
dc.source.issue5
dc.source.volume87
imec.availabilityPublished - open access


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