Adding reconfigurable logic to SOC designs
dc.contributor.author | Gupta, B. | |
dc.contributor.author | Parviainen, J. A. | |
dc.contributor.author | Schaumont, Patrick | |
dc.contributor.author | Tanurhan, Y. | |
dc.contributor.author | Roy, K. | |
dc.date.accessioned | 2021-10-14T16:59:56Z | |
dc.date.available | 2021-10-14T16:59:56Z | |
dc.date.issued | 2001 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/5327 | |
dc.source | IIOimport | |
dc.title | Adding reconfigurable logic to SOC designs | |
dc.type | Journal article | |
dc.source.peerreview | no | |
dc.source.beginpage | 65 | |
dc.source.endpage | 71 | |
dc.source.journal | IEEE Design & Test of Computers | |
dc.source.issue | 4 | |
dc.source.volume | 18 | |
imec.availability | Published - imec | |
imec.internalnotes | DATE 2001 roundtable |
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