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Model for the trap-assisted tunnelling current through very thin SiO2/ZrO2 gate dielectric stacks

dc.contributor.authorHoussa, Michel
dc.contributor.authorStesmans, Andre
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-10-14T17:03:40Z
dc.date.available2021-10-14T17:03:40Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5355
dc.sourceIIOimport
dc.titleModel for the trap-assisted tunnelling current through very thin SiO2/ZrO2 gate dielectric stacks
dc.typeJournal article
dc.contributor.imecauthorHoussa, Michel
dc.contributor.imecauthorStesmans, Andre
dc.contributor.imecauthorHeyns, Marc
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.source.peerreviewno
dc.source.beginpage427
dc.source.endpage432
dc.source.journalSemiconductor Science and Technology
dc.source.issue6
dc.source.volume16
imec.availabilityPublished - imec


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