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Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide

dc.contributor.authorvan Meer, Hans
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-14T18:05:54Z
dc.date.available2021-10-14T18:05:54Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5743
dc.sourceIIOimport
dc.titleThreshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide
dc.typeJournal article
dc.contributor.imecauthorDe Meyer, Kristin
dc.source.peerreviewno
dc.source.beginpage593
dc.source.endpage598
dc.source.journalSolid-State Electronics
dc.source.issue4
dc.source.volume45
imec.availabilityPublished - imec


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