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Toward better wireload models in the presence of obstacles

dc.contributor.authorCheng, C.K.
dc.contributor.authorKahng, A.B.
dc.contributor.authorLiu, Bao
dc.contributor.authorStroobandt, Dirk
dc.date.accessioned2021-10-14T21:14:05Z
dc.date.available2021-10-14T21:14:05Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6104
dc.sourceIIOimport
dc.titleToward better wireload models in the presence of obstacles
dc.typeJournal article
dc.source.peerreviewno
dc.source.beginpage177
dc.source.endpage189
dc.source.journalIEEE Trans. Very Large Scale Integration (VLSI) Systems
dc.source.issue2
dc.source.volume10
imec.availabilityPublished - imec


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