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Phase noise and tuning speed optimization of a 5-500 Mhz hybrid DDS-PLL synthesizer with milli Hertz resolution

dc.contributor.authorClaerhout, Brecht
dc.contributor.authorVandewege, Jan
dc.date.accessioned2021-10-14T21:14:38Z
dc.date.available2021-10-14T21:14:38Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6112
dc.sourceIIOimport
dc.titlePhase noise and tuning speed optimization of a 5-500 Mhz hybrid DDS-PLL synthesizer with milli Hertz resolution
dc.typeBook chapter
dc.source.peerreviewno
dc.source.beginpage93
dc.source.bookRecent Advances in Circuits, Systems and Signal Processing
dc.source.endpage97
imec.availabilityPublished - imec
imec.internalnotesA series of Reference Books and Textbooks, Electrical and Computer Engineering


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