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Optimised n-channel Si/Ge HFETs design for VTH shift immunity

dc.contributor.authorJeamsaksiri, Wutthinan
dc.contributor.authorVelazquez, Jesus Enrique
dc.contributor.authorFobelets, Kristel
dc.date.accessioned2021-10-14T21:54:41Z
dc.date.available2021-10-14T21:54:41Z
dc.date.issued2002-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6435
dc.sourceIIOimport
dc.titleOptimised n-channel Si/Ge HFETs design for VTH shift immunity
dc.typeJournal article
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage2241
dc.source.endpage2245
dc.source.journalSolid-State Electronics
dc.source.issue12
dc.source.volume46
imec.availabilityPublished - open access


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