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High-level cache modeling for 2-D discrete wavelet transform implementations

dc.contributor.authorAndreopoulos, I.
dc.contributor.authorSchelkens, Peter
dc.contributor.authorLafruit, Gauthier
dc.contributor.authorMasselos, K.
dc.contributor.authorCornelis, Jan
dc.date.accessioned2021-10-15T03:58:50Z
dc.date.available2021-10-15T03:58:50Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7136
dc.sourceIIOimport
dc.titleHigh-level cache modeling for 2-D discrete wavelet transform implementations
dc.typeJournal article
dc.contributor.imecauthorSchelkens, Peter
dc.contributor.imecauthorCornelis, Jan
dc.contributor.orcidimecSchelkens, Peter::0000-0003-0908-1655
dc.source.peerreviewno
dc.source.beginpage209
dc.source.endpage226
dc.source.journalJournal of VLSI Signal Processing
dc.source.issue3
dc.source.volume34
imec.availabilityPublished - imec


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