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Electrical characterization, modelling and simulation of MOS structures with high-k gate stacks

dc.contributor.authorAutran, J.L.
dc.contributor.authorMunteanu, D.
dc.contributor.authorHoussa, Michel
dc.date.accessioned2021-10-15T03:59:23Z
dc.date.available2021-10-15T03:59:23Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7160
dc.sourceIIOimport
dc.titleElectrical characterization, modelling and simulation of MOS structures with high-k gate stacks
dc.typeBook chapter
dc.contributor.imecauthorHoussa, Michel
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.source.peerreviewno
dc.source.beginpage251
dc.source.bookHigh-K Gate Dielectrics
dc.source.endpage289
imec.availabilityPublished - imec
imec.internalnotesChapter 3.4


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