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In-line electrical metrology for high-k gate dielectrics deposited by atomic layer CVD

dc.contributor.authorDe Witte, Hilde
dc.contributor.authorPassefort, Sophie
dc.contributor.authorBesling, Wim
dc.contributor.authorMaes, Jan
dc.contributor.authorEason, K.
dc.contributor.authorYoung, Edward
dc.contributor.authorRittersma, Chris
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-10-15T04:24:55Z
dc.date.available2021-10-15T04:24:55Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7459
dc.sourceIIOimport
dc.titleIn-line electrical metrology for high-k gate dielectrics deposited by atomic layer CVD
dc.typeJournal article
dc.contributor.imecauthorMaes, Jan
dc.contributor.imecauthorHeyns, Marc
dc.source.peerreviewno
dc.source.beginpageF169
dc.source.endpageF172
dc.source.journalJournal of the Electrochemical Society
dc.source.issue9
dc.source.volume150
imec.availabilityPublished - imec


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