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High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

dc.contributor.authorOsorio, Roberto
dc.contributor.authorVanhoof, Bart
dc.date.accessioned2021-10-15T05:57:59Z
dc.date.available2021-10-15T05:57:59Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7963
dc.sourceIIOimport
dc.titleHigh speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
dc.typeJournal article
dc.source.peerreviewno
dc.source.beginpage267
dc.source.endpage275
dc.source.journalJournal of VLSI Signal Processing
dc.source.issue3
dc.source.volume33
imec.availabilityPublished - imec


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