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Analysis, modelling and design of chip scale packages (CSPs) for RF and high-speed digital interconnections

dc.contributor.authorChandrasekhar, Arun
dc.date.accessioned2021-10-15T12:50:41Z
dc.date.available2021-10-15T12:50:41Z
dc.date.issued2004-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8668
dc.sourceIIOimport
dc.titleAnalysis, modelling and design of chip scale packages (CSPs) for RF and high-speed digital interconnections
dc.typePHD thesis
dc.source.peerreviewno
dc.contributor.thesisadvisorNauwelaers, Bart
dc.contributor.thesisadvisorMertens, Robert
imec.availabilityPublished - imec


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