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Modelling negative bias temperature instabilities in hole-channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layers

dc.contributor.authorHoussa, Michel
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorAutran, L.
dc.contributor.authorParthasarathy, C.
dc.contributor.authorRevil, N.
dc.contributor.authorVincent, E.
dc.date.accessioned2021-10-15T13:55:29Z
dc.date.available2021-10-15T13:55:29Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9058
dc.sourceIIOimport
dc.titleModelling negative bias temperature instabilities in hole-channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layers
dc.typeJournal article
dc.contributor.imecauthorHoussa, Michel
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.source.peerreviewno
dc.source.beginpage2786
dc.source.endpage2791
dc.source.journalJournal of Applied Physics
dc.source.issue5
dc.source.volume95
imec.availabilityPublished - imec


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